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Lecturer(s)
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Konečný Jiří, Ing. Ph.D.
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Marek Josef, Ing. CSc.
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Course content
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Introduction, history of programmable logic devices (PLD). Basic properties and types of PLD, architecture differencies. Hardware description languages (HDL) survey: ABEL, VHDL, Introduction to VHDL, hierarchical v. flat design. Combinational logic function realization in VHDL, implementation Sequential logic circuit description and realization, state machines. Internal architecture of PLD, SPLD, CPLD, FPGA. Design and testing tools, Altera, Xilinx, Lattice. Configuration and testing of PLD, configuration device. Intelectual property (IP) blocks and tools, Altera SOPC, NIOS. Sample designs.
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Learning activities and teaching methods
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Monologic (reading, lecture, briefing), Dialogic (discussion, interview, brainstorming), Laboratory work
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Learning outcomes
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To acquaint students with basics of VHDL,Verilog and basic procedures inPLD design, next with principles, architecture and applications of PLD (FPGA), accent is put on methods of all the schematic and HDL design description and simulation,debugging and testing-verification of design to implementation to target device. In practical part there are a few projects:light signal Reaction tester (with functional components: 7-segment display decoder, counters, PLL, FSM), next simple interconnection ADC to DAC with signal generator and osciloskop verification, next AM modulator in MHz band and finally frequency filter FIR verified by Spectral analyser. as a intro students pass 1-hour intruductory test followed by explanation of right answers to test questions.
Elementary knowledge from the field of HDL and PLD.
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Prerequisites
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Basic knowledge of digital technics and digital integrated circuits.
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Assessment methods and criteria
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Oral examination, Written examination
Excercise attendance, semestral work.
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Recommended literature
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Kanilo, K. VHDL for Programmable Logic. Prentice Hall, New York, 1996.
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Kolouch, Jaromír. Programovatelné logické obvody : přednášky. Brno: Vysoké učení technické v Brně, 2002. ISBN 80-214-2196-7.
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Kolouch, Jaromír. Programovatelné logické obvody a návrh jejich aplikací v jazycích ABEL a VHDL : počítačové cvičení. Brno: Vysoké učení technické v Brně, 2002. ISBN 80-214-2197-5.
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