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Lecturer(s)
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Course content
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Introduction, history of programmable logic devices (PLD). Basic properties and types of PLD, architecture differencies. Hardware description languages (HDL) survey: ABEL, VHDL, Introduction to VHDL, hierarchical v. flat design. Combinational logic function realization in VHDL, implementation Sequential logic circuit description and realization, state machines. Internal architecture of PLD, SPLD, CPLD, FPGA. Design and testing tools, Altera, Xilinx, Lattice. Configuration and testing of PLD, configuration device. Intelectual property (IP) blocks and tools, Altera SOPC, NIOS. Sample designs.
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Learning activities and teaching methods
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unspecified, Monologic (reading, lecture, briefing), Work with text (with textbook, with book), Methods of individual activities, Skills training, Laboratory work
- Home preparation for classes
- 40 hours per semester
- Preparation for an exam
- 45 hours per semester
- Contact teaching
- 35 hours per semester
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Learning outcomes
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The course provides to students with Programmable Logic Devices. Introduction in internal architecture of PLD, logic function. Requirements that will be announced by the teacher at the first lecture: participation in seminars is mandatory, two absences are tolerated, for credit you must pass a mid-semester and semester test.
Students are able to orientate in Programmable Logic Devices.
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Prerequisites
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To acquaint students with basics of VHDL,Verilog and basic procedures inPLD design, next with principles, architecture and applications of PLD (FPGA), accent is put on methods of all the schematic and HDL design description and simulation,debugging and testing-verification of design to implementation to target device. In practical part there are a few projects:light signal Reaction tester (with functional components: 7-segment display decoder, counters, PLL, FSM), next simple interconnection ADC to DAC with signal generator and osciloskop verification, next AM modulator in MHz band and finally frequency filter FIR verified by Spectral analyser. as a intro students pass 1-hour intruductory test followed by explanation of right answers to test questions. Elementary knowledge from the field of HDL and PLD.
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Assessment methods and criteria
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Oral examination, Written examination, Home assignment evaluation, Student performance assessment, Self project defence
During the semester and in the final exam, the student must demonstrate an understanding of the solved problems in the scope of the studied subject.
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Recommended literature
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Kanilo, K. VHDL for Programmable Logic..
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Kanilo, K. VHDL for Programmable Logic.. New York, 1996.
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Kolouch, J. Programovatelné logické obvody : přednášky.
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Kolouch, J. Programovatelné logické obvody : přednášky. Brno, 2002. ISBN 80-214-2196-7.
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Kolouch, J. Programovatelné logické obvody a návrh jejich aplikací v jazycích ABEL a VHDL : počítačové cvičení..
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Kolouch, J. Programovatelné logické obvody a návrh jejich aplikací v jazycích ABEL a VHDL : počítačové cvičení.. Brno, 2002. ISBN 80-214-2197-5.
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Pinker, J., Poupa, M. Číslicové systémy a jazyk VHDL.
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Pinker, J., Poupa, M. Číslicové systémy a jazyk VHDL. Praha, 2006. ISBN 80-7300-198-5.
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