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Course info
KE / RNLOE
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Course description
Department/Unit / Abbreviation
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KE
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RNLOE
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Academic Year
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2023/2024
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Academic Year
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2023/2024
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Title
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Programmable Logic Circuits
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Form of course completion
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Examination
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Form of course completion
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Examination
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Accredited / Credits
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Yes,
4
Cred.
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Type of completion
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Combined
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Type of completion
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Combined
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Time requirements
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Seminar
20
[Hours/Semester]
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Course credit prior to examination
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Yes
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Course credit prior to examination
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Yes
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Automatic acceptance of credit before examination
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No
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Included in study average
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YES
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Language of instruction
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Czech
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Occ/max
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Automatic acceptance of credit before examination
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No
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Summer semester
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0 / -
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1 / -
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0 / 0
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Included in study average
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YES
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Winter semester
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0 / -
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0 / -
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0 / -
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Repeated registration
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NO
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Repeated registration
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NO
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Timetable
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Yes
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Semester taught
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Summer semester
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Semester taught
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Summer semester
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Minimum (B + C) students
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not determined
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Optional course |
Yes
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Optional course
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Yes
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Language of instruction
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Czech
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Internship duration
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0
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No. of hours of on-premise lessons |
0
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Evaluation scale |
A|B|C|D|E|F |
Periodicity |
každý rok
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Evaluation scale for credit before examination |
S|N |
Periodicita upřesnění |
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Fundamental theoretical course |
No
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Fundamental course |
No
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Fundamental theoretical course |
No
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Evaluation scale |
A|B|C|D|E|F |
Evaluation scale for credit before examination |
S|N |
Substituted course
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None
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Preclusive courses
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N/A
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Prerequisite courses
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N/A
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Informally recommended courses
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N/A
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Courses depending on this Course
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N/A
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Histogram of students' grades over the years:
Graphic PNG
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XLS
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Course objectives:
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The course provides to students with Programmable Logic Devices. Introduction in internal architecture of PLD, logic function.
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Requirements on student
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During the semester and in the final exam, the student must demonstrate an understanding of the solved problems in the scope of the studied subject.
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Content
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Introduction, history of programmable logic devices (PLD). Basic properties and types of PLD, architecture differencies. Hardware description languages (HDL) survey: ABEL, VHDL, Introduction to VHDL, hierarchical v. flat design. Combinational logic function realization in VHDL, implementation Sequential logic circuit description and realization, state machines. Internal architecture of PLD, SPLD, CPLD, FPGA. Design and testing tools, Altera, Xilinx, Lattice. Configuration and testing of PLD, configuration device. Intelectual property (IP) blocks and tools, Altera SOPC, NIOS. Sample designs.
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Activities
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Fields of study
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Kolouch, J. Programovatelné logické obvody : přednášky. Brno: Vysoké učení technické v Brně, 2002. ISBN 80-214-2196-7.
Kolouch, J. Programovatelné logické obvody a návrh jejich aplikací v jazycích ABEL a VHDL : počítačové cvičení. Brno: Vysoké učení technické v Brně, 2002. ISBN 80-214-2197-5.
V případě mimořádných opatření bude výuka probíhat vzdáleně s využitím programu MS Teams v době dle rozvrhu. Účast na schůzkách skupiny v MS Teams je ekvivalentní účasti na přednáškách a cvičeních.
In the case of distance learning, lessons will be tought trough MS Teams. Lessons will be at the time shown in the timetable. MS Teams is equivalent to participation and or attendens in lectures and excersises.
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Guarantors and lecturers
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Literature
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Basic:
Pinker, J., Poupa, M. Číslicové systémy a jazyk VHDL. Praha, 2006. ISBN 80-7300-198-5.
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Basic:
Kolouch, J. Programovatelné logické obvody : přednášky. Brno, 2002. ISBN 80-214-2196-7.
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Basic:
Kanilo, K. VHDL for Programmable Logic.. New York, 1996.
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Recommended:
Pinker, J., Poupa, M. Číslicové systémy a jazyk VHDL.
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Recommended:
Kolouch, J. Programovatelné logické obvody : přednášky.
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Recommended:
Kolouch, J. Programovatelné logické obvody a návrh jejich aplikací v jazycích ABEL a VHDL : počítačové cvičení..
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Recommended:
Kolouch, J. Programovatelné logické obvody a návrh jejich aplikací v jazycích ABEL a VHDL : počítačové cvičení.. Brno, 2002. ISBN 80-214-2197-5.
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Recommended:
Kanilo, K. VHDL for Programmable Logic..
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Time requirements
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All forms of study
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Activities
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Time requirements for activity [h]
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Domácí příprava na výuku
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40
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Kontaktní výuka
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35
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Příprava na zkoušku
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45
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Total
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120
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Prerequisites - other information about course preconditions |
To acquaint students with basics of VHDL,Verilog and basic procedures inPLD design, next with principles, architecture and applications of PLD (FPGA), accent is put on methods of all the schematic and HDL design description and simulation,debugging and testing-verification of design to implementation to target device. In practical part there are a few projects:light signal Reaction tester (with functional components: 7-segment display decoder, counters, PLL, FSM), next simple interconnection ADC to DAC with signal generator and osciloskop verification, next AM modulator in MHz band and finally frequency filter FIR verified by Spectral analyser. as a intro students pass 1-hour intruductory test followed by explanation of right answers to test questions.
Elementary knowledge from the field of HDL and PLD.
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Competences acquired |
Students are able to orientate in Programmable Logic Devices. |
Teaching methods |
- Přednášení
- Monologic (reading, lecture, briefing)
- Work with text (with textbook, with book)
- Methods of individual activities
- Skills training
- Laboratory work
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Assessment methods |
- Oral examination
- Written examination
- Home assignment evaluation
- Student performance assessment
- Self project defence
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